1. Technical Field
This invention generally relates to Level Sensitive Scan Design (LSSD) circuits, and more specifically relates to low power LSSD flip flops and a flushable single clock splitter for flip flops.
2. Background Art
Flip Flops are common devices that are used to allow data to be latched and propagated. A common type of D Flip Flop (DFF) apparatus is shown in FIG. 8. DFF apparatus 600 comprises a multiplexor (MUX) 610 having outputs 611, a Master Latch (ML) 620 having outputs 613 and 614, and a Slave Latch (SL) 630 having a Scan Out (SO) output. The ML is often referred to as latch "L1" and the SL is often referred to as latch "L2". DFF apparatus 600 also comprises a Scan In (SI) input, a Scan Enable (SE) input, a Data (D) input, and an Edge (E) clock input. The MUX 610 has an inverter I1 and two drivers D1 and D2. The ML 620 has inverters I7, I2, I3, and I8, and transistors T1 and T2. The SL 630 has inverters I4, I5, and I6 and has transistors T5, T6, and T7. The SE signal determines whether data input or scan in input information will be latched into the ML, and the edge clock determines when the output 611 will be latched. As is known in the art, by connecting the SO of one DFF apparatus with the SI of another DFF apparatus, data may be serially passed through many of these apparatuses.
Thus, the DFF apparatus of FIG. 8 is functional yet allows some testing. To improve on the testing aspect of these devices, Level Sensitive Scan Design (LSSD) was implemented. LSSD is a design methodology that allows many elements to be functionally tested before a semiconductor chip is used. In particular, for DFF apparatuses, three clocks are used for LSSD: the A, B, and C clocks. Each of these clocks provide certain testing benefits, which will be discussed in reference to the next figures.
In FIG. 9, another prior art DFF apparatus 900 is shown. In this apparatus 900, the ML (latch L1) 920 has an output 911 that is the input to the SL (latch L2), which has its own scan out output. Clock splitter 940 comprises a NAND gate and three AND gates. Generally, there would be one clock splitter 940 for many DFF apparatuses, and the ZB and ZC clocks would be distributed to these apparatuses. The MLE is a Master Latch Enable that allows the ML to be enabled independently from the SL. The EN is an enable signal that enables the edge (E) clock to propagate to both the ML and the SL. The A clock causes data on the SI input to be latched into the ML. The B clock causes data on the output 911 to be latched from the ML to the SL. The C clock causes data on the D input to be latched into the ML. Thus, the LSSD implementation of a DFF, as shown in FIG. 9, allows the DFF apparatus' function to be tested yet allows normal operation.
The DFF apparatus 900 of FIG. 9 provides a further testing operation called a flush. In a flush, data is transferred directly from the SI input to the SO output. When A=B=1, or a high logic value, a scan flush is enable that "flushes" data from the SI input to the SO output.
In FIG. 10, another DFF apparatus 1000 is shown. This apparatus 1000 is identical to the DFF apparatus of FIG. 8 except in the clocking of the L1 and L2 latches. To support the flush operation, this DFF apparatus 1000 comprises a slightly different clock splitter 940. In particular, an OR gate is used instead of the third AND gate of FIG. 9 and the A clock is used in place of the MLE. When A=B=1 or a logic high value and C=0 or a logic low value, a scan flush is enabled that "flushes" data from the D input to the SO output (if SE=0) or from the SI input to the SO output (if SE=1).
One of the advantages that the apparatuses of FIGS. 9 and 10 have over the apparatus of FIG. 8 is that operation using test clocks A, B, and C is independent of layout or other timing-related parameters, provided that the individual test clock pulses are sufficiently separated in time from each other.
Unfortunately, there are certain problems associated with these DFF apparatuses. What is needed are flip flops and a flushable single clock splitter for flip flops that overcome these problems.